HPEST

  Advanced Training in High Performance Embedded Systems

 

Venue:  Hotel Slovenska Plaza****, Budva, Montenegro
Date: 09. 06-14. 06. 2019
Description:  The training is intended for all those who want to acquire real-life knowledge from advanced embedded systems. The equivalent load of the 5 days training seminar is 3 ECTS credits. The main topics are: Recent challenges in Embedded computing, Cyber Physical and Internet of Things design, advanced FPGA design, Cutting-edge DSP processors, Code Optimization, Real-time operation systems, Real-time signal and image processing. Most lessons will be followed with practicexercises. The detailed agenda is given bellow, while more information could be obtained by Profs:

Naim Dahnoun and Dr. Sergey Vityazev (Naim.Dahnoun@bristol.ac.uk ,  vityazev.s.v@tor.rsreu.ru ).

Price:  The training fee is  €350. The accommodation prices in Slovenska Plaza for FB are:  in 3* hotel €36 in 1/ 2 room and €43 in  1/ 1 room; in  4**** hotel 39,00€ in 1/ 2 room and  €45 in 1/ 1. The Excursion costs around €30 per person and the conference dinner  €40 (not compulsory) per person. You can arrange the accommodation and social life by yourself (the fee is only compulsory).

PROGRAMME (and CFP, pls downolad)
 
Instructors:

Prof. Lech Jóźwiak, Eindhoven University of Technology, with Radovan Stojanovic one of the MECO’s establishers,  about Prof. Jóźwiak .

 

 

Prof Radovan Stojanovic, University of Montenegro, Together with Lech Jóźwiak establisher of projects www.embeddedcomputing.me   and MECO. One of the pioneers of the FPGA and SoC design at Balkan.    about Prof. Stojanovic  in Wikipedia.

 

Prof. Naim Dahnoun, Bristol University: the textbooks by Prof. N. Dahnoun ,  Digital Signal Processing Implementation and Multicore DSP: From Algorithms to Real-time Implementation on the TMS320C66x SoC . About Prof. N. Dahnoun .

 

 

Dr Sergey Vityazev , Senior Lecturer – Ryazan State Radio Engineering University, about Dr Vityazev.  Teaching multi-core DSP implementation on EVM C6678 board.

 

 

Prof. Dr. Betim Çiço, Epoka University, Tirana, Pioneer and long lasting contributions in fields of Advance Computer Architecture, Digital Electronics, FPGA, Artificial Intelligence and Robotics, etc in Albania and Western Balkan. About Prof. B. Cico .

 

Notes:
Note 1: Real-time Operating System, TI-RTOS (SYS/BIOS):  This lecture is divided into three main sections: (1) Real-time scheduler that is composed of the hardware and software interrupts; the task, the idle, clock and timer functions, synchronisation and events, (2) the Dynamic Memory Management and (3) laboratory experiments.
Note 2: Software Optimisation, Linear Assembly, Interfacing C and Assembly: This lecture discusses the different levels of optimisation for multicore and shows how code can be optimised for a DSP core. This lecture also shows how to use intrinsics and interface C language with intrinsics and assembly code. Multiple examples showing how to optimise code by hand and using the tools are provided.
Note 3: FPGA:  A field-programmable gate array is an integrated circuit designed to be configured by a customer or a designer in the process of prototyping. The FPGA configuration is generally specified using a hardware description language (VHDL or Verilog). In some sense it is intermediate phase in designing/manufacturing an application-specific integrated circuit (ASIC). The preparation phases before configuration is text description entry or block diagram (schematic) entry.
Note 4:  GPUs- Graphics Processing Units, DNNs: Deep Neural Networks
Note 5: DSP processors:  are specialized microprocessors or microcontrollers, with its architecture optimized for signal processing tasks.

Submission steps:

1. Subscribe to the Chairs of the training by sending email with basic data.

Your subscription>>

2. You will get an answer about whether your application is approved or not.

3. Register via MECO registration system. 

4. Follow further instructions from the Chairs and from Web. 

Registrations are limited and will be handled on a first-come, first-served basis. no later than 31.01.2019.