APEG Group: Teaching Resources
Dear Students, Engineers, Researchers and Hobbyists,
Welcome to the website of the Applied Electronics Group (APEG), Faculty of Electrical Engineering, University of Montenegro. APEG Group (Applied Electronics Group) was founded in 2004 at Faculty of Electrical Engineering, University of Montenegro. It deals with electronics applied anytime everywhere. In addition to teaching content of the different courses, the site can be interesting for everyone dealing with HW and SW, including many aspects.
I hope you will find something interesting for you on our site.
Yours,
Prof. dr Radovan Stojanovic, APEG establisher and responsible professor for courses
<Teaching Courses> <Research> <Other>
COURSES:
Medical Electronics (MEDEL), BSc, Spec and Msc
Automated Design of Electronic Circuits and Systems (APEKS) and Simulation of Electronic Circuits (SEK), Spec and MSc
Industrial Electronics (INDEL), Spec and MSc
Real Time Control (RTC), Spec and MSc
Hardware-Software Design (HW-SW-DES), MSc
Biomedicinka mjerenja i instrumentacija (BMMI), MSc
VHDL and VHDL Programming, Spec and MSc
C Programing Language, BSc level
Applications of GIS Technologies in Maritime (GIS-MA), Spec and MSc
Modeling and Simulation in Electronics (MSE), Spec and MSc
Technological Entrepreneurship (TeEn), PhD
Precision Agriculture (PA), PhD
IoT Ecosystems (IoT-ECO), PhD
Archive from the old site
NEWS:
Septembar 2024, ispiti, rezultati
Mole se studenti da provjere rezultate i u slucaju potrebe kontaktiraju predmetnog nastavnika
Rspored nastave za predmete Grupe
– PETAK: 16:15, UURV, Lab za Elektroniku ili sala Gepsus
– UTORAK: 16:15, HW-SW-DES, Lab za Elektroniku ili sala Gepsus
– CETVRTAK: 16:15, BMMI, Lab za Elektroniku ili sala Gepsus
– UTORAK: 12:15, VHDL Programiranje, Lab za Elektroniku ili sala Gepsus
– PONEDELJAK: 09:15, APEKS & SEK, Lab za Elektroniku ili sala Gepsus
- MEDEL (Medical Electronics):
NEWS:
Staff and term:
Prof. dr Radovan Stojanovic (professor), Dr Dejan Karadaglic (deputy), Summer semester
Lessons:
ECTS catalogue
Lessons from professor
Labs and Exercises:
Workflow of the classes and exams:
Progress and knowledge check:
Other (additional material etc..):
Literature:
Links:
Assistan’s space (teaching and other material from assistant)
- APEKS and SEK (Automatised Design of Electronic Circuits and Systems and Simulation of Electronic Circuits):
NEWS:
Staff and term:
Prof. dr Radovan Stojanovic (professor), Dr Dejan Karadaglic (deputy), Summer semester
Lessons:
Part I: VHDL and FPGA Design (Pressentations for students)
AUTOMATIZOVANO PROJEKTOVANJE DIGITALNIH SISTEMA (VHDL i FPGA), Radovan Stojanovic, Textbook, Tempus, 2008, Book in Serbian
Part II: Lesson 1 (The tools for simulation of analog circuits)
9_1_Quartus_free, Tool for development, Editor, Compiler, Simulator, Programmer, former Altera, now Intel
Exercises and Lab:
- Simulacione vjezbe: Vjezbe #1-#7 u okvuru predavanja Part I: VHDL and FPGA Design
- Laboratorija, priprema: Vjezbe1-3, Vjezbe4-7
- UART Coomunication on DE1, cores, IP cores academic programme, example 1, example 2, SOPC Builder
- LAB1_MATERIAL (The colection of the programmes in Quartus 9.1)
Workflow of the classes and exams:
Rules (scores, max 100):
presence: 5; activity: 10, lab.1-mini seminar: 30 (15 in group 15 in person), lab 2-mini seminar:30(15 in group, 15 in person), final: 25 (in person)
in person: problem solving
Progress and knowledge check:
Progress_2024_regular
Progress_2024_others
Other (additional material etc..):
- Radovi studenata, seminarski, tehnicki Link…
- Traffic_light_controller_on_FPGA_DE2-70_board
- Two_Digit_Seven_Segment_Counter
- Up_counter_with_7_segment_display
- Frequency_counter_design
- 2_digit_7_segment_counter
- Seven_segment_counter_ 0 – 99
- Step_Stair_Light_Timer_with_FPGA
- LED_intensity_control_using_PWM
- Blink_circuit_with_3_to_8_Decoder
- Ring_Johnson_counter
- Real_car_alarm_2
- Real_car_alarm
- Stair_Steps_Light_timer
- Simple_calculator_on_FPGA_DE2-70 board
- Simple_keyboard_with_four_keys
- Deboucing_on_FPGA
- RANDOM_NUMBER_GENERATOR_FPGA
- Generator_function_on_FPGA
- Multi_chanels_PWM_controler_on_FPGA
- Lotto_Generator_FPGA
- Real car-dor alarm Wwth Panic button
- FPGA DESIGN OF STOPWATCH (template, ResearchGate)
- DC Motor Control Using FPGA Generated PWM (template, ResearchGate)
- MATLAB to VHDL Converter Examples (template, ResearchGate)
- IIR filter design in FPGA -Simple example (template, ResearchGate)
- Literature:
- K.L. Short, VHDL for Engineers
- Pong P. Chu, FPGA Prototyping by VHDL Examples: Xilinx Spartan™-3 Version, July 2007, DOI: 10.1002/9780470231630, ISBN: 9780470185315
- Ian Grout, Digital Systems Design with FPGAs and CPLDs,
- EEC 180B – Digital Systems II, University of California, Davis, https://www.ece.ucdavis.edu/~soheil/teaching/EEC180B-S06/labs.html
- On_Line Tool (za vjezbanje)
- Download Software Page Intel Quartus,
- Download 91_quartus_free
- University Program (Terasic)
- https://www.newark.com/pdfs/techarticles/microchip/3_3vto5vAnalogTipsnTricksBrchr.pdf
Links:
Assistan’s space (teaching and other material from assistant)
- INDEL (Industrial Electronics):
NEWS:
Staff and term:
Prof. dr Radovan Stojanovic (professor), Dr Dejan Karadaglic (deputy), Summer semester
Lessons:
Labs and Exercises:
Workflow of the classes and exams:
Progress and knowledge check:
September term 2024 results
Other (additional material etc..):
Literature:
Links:
Assistan’s space (teaching and other material from assistant)
- RTC (Real Time Control):
NEWS:
Staff and term:
Prof. dr Radovan Stojanovic (professor), Dr Dejan Karadaglic (deputy), Summer semester
Lessons:
ECTS catalogue
Lessons 2024
Resursi PLC
Workflow of the classes and exams:
Progress and knowledge check:
Checking methodology: prisustvo 5, aktivnost 10, LAB 1: 10 poena, LAB 2: 10 poena, Seminarski : 35, Zavrsni (usmeni) 30
Progress_MS_2024
Other (additional material etc..)
Labs and Exercises:
Lab #1: Input, CPU, Output. Pooling, Interrupts. Open and close loop control. (10 poena): LAB A-B
Procitati: Predavanja i Vjezbe 1-6 iz Lessons 2024. Primjeri radova na ovu temu se mogu naci na Dodatni materijal za LAB_AB
Izvjestaj za realizovanju laboratorije: Potrebno je napraviti izvestaj sa realizovane laboratorije prema datom Primjeru izvjestaja
Lab #2: LAB-C, LAB-D (RTOS and Energy Meter), 10 points, Work in 3 groups. Each of groups is obligated to perform Vjezba #1 or Vjezba #2 from LAB-C and Vjezba #1 from LAB-D
- Dodatni materijal za LAB_AB
- Ocitavanje temperature i sile na udaljenom Arduinu, The measurement of temperature and force using Arduino and Serial Terminal
- Hardverski interapti – Arduino, primjeri Hardware Interrupts on Arduino, examples
- Ocitavanje temperature i sile, timer interrupt Sampling the temperature and the force by using timer interrupt
- On-Off Regulator Temperature , On-Off Temperature Regualtor
- Automatska regulacija svijetla, On-Off Light regulator
- PWM Regulator of DC motor
- Koristenje Terminal Emulatora za zadavanje komandi
- Izvrsni organ sa synhro kolom i triackom (ne radi link)
- https://www.youtube.com/watch?v=mYaYHA_ZnZs (poling metod)
- https://www.youtube.com/watch?v=vMsmNQvjcNI&t=5s (interrupt metod)
- https://www.youtube.com/watch?v=Eflh6BsH4i4 (povezivanje Arduina na Vernier sensore)
- Interrupt tutorial
- Example of timer and serial event interrupt (Arduino code) (ne radi)
- Temperature measurement by thermocouple and Arduino
- Dynamo meter by Arduino
- Temperature measurement by Arduino
- PH measurement by Arduino (ne radi)
- Optical intensity measurement by Arduino (ne radi)
- Current measurement by shunt and Arduino (ne radi)
Seminarski 2024:
Grupa 1: Experimental SCADA system FREE SCADA + 1-2 panel control of simple system as example temperature controler.
Grupa 2: Experimental SCADA system FREE SCADA + 1-2 panel control of simple system as example ligh or level or entrance controler.
Potrebno je instalirati besplatnu SCADU za edukaciju. Naci je na Internetu. Povezati je sa PCL om koji ima prosti ulaz (senzor temperature ili neke druge velicine) i prosti izlaz on-off rele. Ulaz sa senzora se dovodi na PLC iz kojeg se vrsi upravljanje relea. PLC je povezan na SCADA Panel. Npr. Projektujemo panel za kontrolu temperature, koji prikazuje trenutnu i zadatu temperaturu i pri tom komunicira sa PLC za prikupljanje podataka, startovanje i stopiranje programa. PLC vrsi regulaciju temperature i komunikaciju sa panelom. Vidi sliku.
Primjer seminarskih
- Lazar Ašanin, Ivan Adžić, Ognjen Bulatović, Miloš Bojić, Semir Kardović and Pavle Saveljić and Radovan Stojanović, Smart Energy Meter with Arduino, Technical Report, 2023
- Uroš Janković, Ivan Dušević, Balša Kruščić, Božidar Ašanin, Tomislav Markićević, Jovana Bovan and Radovan Stojanovic, Staircase lighting automata using Siemens LOGO!, Technical Report, 2023.
Literature:
Links:
Assistan’s space (teaching and other material from assistant)
- HW-SW-DES (Hardware – Software Design):
NEWS:
Staff and term:
Prof. dr Radovan Stojanovic (professor), Dr Dejan Karadaglic (deputy), Summer semester
Lessons:
Introduction
Labs and Exercises:
I group: Smart parking (diy loop sensor, diy 555 based metal detector, link)
1. Milica Rajcic, B
2. Dragana Zoric, B
3. Andjela Pantovic, B
4. Andjela Ikovic,B
5. Sara Milinkovic, B
6. Lazar Popovic, B
II grupa: (Kethosis Detection)
1. Azra Rastoder, B
2. Milica Bakrac, B
3. Dubravka Scekic, B
4. Stanka Miseljic, B
5. Tamara Rakocevic, B
6. Ivana Loncar, B
7. Ajka Catovic,B
8. Elza Chibrak,B
III grupa: (diy capacitive sensor)
1. Vasilije Spalevic, D
2. Tamara Andjusic, D
3. Stefan Zivkovic, C
4. Sario Arnautovic, D
5. Bozo Bozovic, C
IV Grupa (JavaScript Applet za L calaculation, link)
Workflow of the classes and exams:
Progress and knowledge check:
Other (additional material etc..):
Literature:
Links:
Assistan’s space (teaching and other material from assistant)
- BMMI (Biomedical Measurements and Instrumentation):
NEWS:
Staff and term:
Prof. dr Radovan Stojanovic (professor), Dr Dejan Karadaglic (deputy), Summer semester
Lessons:
Introduction and tasks
Labs and Exercises:
Workflow of the classes and exams:
Progress and knowledge check:
September term 2024 results
Other (additional material etc..):
Literature:
Links:
Assistan’s space (teaching and other material from assistant)
- VHDL language and VHDL Programming
NEWS:
Staff and term:
Prof. dr Radovan Stojanovic (professor), Dr Dejan Karadaglic (deputy), Summer semester
- Lessons:
- VHDL and FPGA
- AUTOMATIZOVANO PROJEKTOVANJE DIGITALNIH SISTEMA (VHDL i FPGA), Radovan Stojanovic, Textbook, Tempus, 2008, Book in Serbian
- 9_1_Quartus_free, Tool for development, Editor, Compiler, Simulator, Programmer, former Altera, now Intel
- Video startup from teacher, How to start Quartus and perform simple example.
- Labs and Exercises:
- Exercises: within lessons VHDL and FPGA, Oznacene kao Vjezba #1 – Vjezba #7, Code, kompalacija, simulacija
- Labs: Exercises1-4, Exercises4-6, Code, kompalacija, simulacija, assigments, programming board, verification of the funkcionality on the board
- LAB I: Exercises 1,2,3 (Exercises1-4) and 4,5 (from Exercises4-6,). Work in groups 5 students per table, 2 tables.
- Material for Labs:
- DE2-70 Pins AsigmentsDE2-70,
- User Manual
- CD-ROM-DE2-70
- Workflow of the classes and exams:
- D1 Prisustvo (5)
- D2 Kolokvijum I (35)
- Pismeni (25). Asistent. Zadaci iz pripremnog materijala , dio A i dio B, zadatak iz dijela A nosi 40% od 25, dok zadatak iz dijela B nosi 60% od 25 (SPR Dio A (1-27), dio B (1-20)). Broj zadatka iz oba dijela se random odredjuje iz testnog materijala (koji je slican pripremnom, ali u pojedinim zadacima, brojne vrijednosti ili neki uslovi mogu biti promijenjeni) prije starta kolokvijuma. Zadaci se predaju preko forme za predaju. Trajanje kolovijuma je 60min.
- D2.1 Pripremni materijal, pismeni (25)
- Broj zadatka iz oba dijela se random odredjuje, prije starta kolokvijuma. Zadaci se predaju preko forme za predaju. Trajanje kolovijuma je 60min.
- Pripremni materijal (SPR Dio A (1-27), dio B (1-20))
- Primjer predaje kolokvijuma
- Primjer dobre izrade, sa rjesenjem
- Primjer gresaka
- Upustvo nastavnika (video), Upustvo za pokretanje programa i izradu primjera
- Testni materijal (neposredno prije kolokvijuma)
- Raspored zadataka (neposredno prije kolokvijuma)
- Predati faj pod nazivom APEKS_SEK_2022_Kol1_Jovana_Cipranic.pdf
- Trajanje 90 min.
- Link za predaju Kolokvija 8. April 2024.
- Zadaci za 8. April 2024
- Rezultati kolokvijuma od 8. Aprila 2024.
- D2.2 Pripremni materijal, usmeni (10). Nastavnik.
- Jedno (1) pitanje, kviz, (5 poena) iz testnog materijala, Primpremni materijal C 2023 , jedno (1) pitanje (5 poena) iz gradiva. Testni materijal na ispitu je izmijenjen u pogledu sprecavanja copy-paste (5 bodova). Jedno pitanje od strane nastavnika iz materijala za predavanje (5 poena), oznaceno sa “C1” u predavanjima.
- D3 Laboratorija (20). Asistent
- Rad u grupama na prakticnim vjezbama, Exercises1-4, Exercises4-6, (10 poena). Provjera od strane asistenta (10 poena)
- Primjer predaje Laboratorije koja se predaje preko sistema sa imenom fajla kakav je dat, obratiti paznju na video koji mora pratiti prezentaciju, na kraju opisa je dat link na video… Primjer opisa vjezbe
- D4 Zavrsni (40)
- D4.1 Pripremni materijal, pismeni (10). Asistent
- 1 zadatak (10 poena) iz dijela A + B pripremnog materijala, koji se nalazi ovdje (Materijal je apdejtovan 16. januara 2024 – Dejan Karadaglić).
- D4.2 Pripremni materijal, usmeni (30). Nastavnik.
- 1 kviz pitanje(10 poena) iz dijela C, pripremnog materijala . 2 pitanje profesora iz gradiva (2×10) poena, iz materijala za predavanje
Progress and knowledge check:
Progress of the students 2024
Other (additional material etc..):
Dodatni materijal (ranije generacije, laboratorija i ostali radovi)
- Implementation of VHDL-FPGA Circuits in DE-70 Board (The files with the bellow titles Link…)
- Traffic_light_controller_on_FPGA_DE2-70_board
- Two_Digit_Seven_Segment_Counter
- Up_counter_with_7_segment_display
- Frequency_counter_design
- 2_digit_7_segment_counter
- Seven_segment_counter_ 0 – 99
- Step_Stair_Light_Timer_with_FPGA
- LED_intensity_control_using_PWM
- Blink_circuit_with_3_to_8_Decoder
- Ring_Johnson_counter
- Real_car_alarm_2
- Real_car_alarm
- Stair_Steps_Light_timer
- Simple_calculator_on_FPGA_DE2-70 board
- Simple_keyboard_with_four_keys
- Deboucing_on_FPGA
- RANDOM_NUMBER_GENERATOR_FPGA
- Generator_function_on_FPGA
- Multi_chanels_PWM_controler_on_FPGA
- Lotto_Generator_FPGA
- FPGA DESIGN OF STOPWATCH (template, Researchgate)
- DC Motor Control Using FPGA Generated PWM (template, Researchgate)
- MATLAB to VHDL Converter Examples (template, Researchagate)
- IIR filter design in FPGA -Simple example (template, Researchgate)
- EEC 180B – Digital Systems II, University of California, Davis, https://www.ece.ucdavis.edu/~soheil/teaching/EEC180B-S06/labs.html
- FPGA Prototyping by VHDL Examples: Xilinx Spartan™-3 Version, July 2007, DOI: 10.1002/9780470231630, ISBN: 9780470185315
Literature:
Links:
Assistan’s space (teaching and other material from assistant)
RESEARCH: